Leakage Power Minimization Techniques In CMOS Inverter Circuits
DOI:
https://doi.org/10.54388/jkues.v4i4.361Keywords:
CMOS Inverter, Power Dissipation, Static power reduction, Stack technique, LECTOR, LC P/N MOS, VLSI DesignAbstract
Power efficiency has become a paramount design constraint in modern CMOS integrated circuits, particularly as technology scaling leads to significant static power dissipation due to leakage currents. This work presents a comprehensive evaluation and implementation of three prominent leakage-reduction techniques: Forced Transistor Stacking (FTS), Leakage Control Transistor (LECTOR), and Leakage-Control P/N MOS (LC P/N MOS). These techniques are implemented for a CMOS inverter circuit using DSCH and Microwind 2.6 design tools in a 120nm CMOS process. The methods are systematically compared in terms of leakage power suppression, propagation delay, and area overhead. Simulation results demonstrate that the LC P/N MOS technique achieves a remarkable 99.98% reduction in static power dissipation compared to a standard inverter, albeit with a slight increase in delay. The LECTOR technique offers the best performance with a mere 5ps delay, while the Stack technique provides a balanced trade-off. The findings provide clear guidelines for selecting Leakage reduction strategies based on application-specific requirements of power, performance, and area.
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